Method and architecture for fast flash memory programming
US7505328B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Aug 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.