Scanned memory testing of multi-port memory arrays
US7506225B2 · kind B2 · utility
4Cited by
17References
9Claims
0Family size
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Key dates
| Filing date | Oct 14, 2005 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Apr 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.