Methods of mapping a logical memory representation to physical memory in a programmable logic device
US7506298B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-implemented methods of mapping a logical representation of a memory to physical memory, e.g., in a programmable logic device (PLD). The logical representation of the memory is input into the computer, which generates an initial solution (e.g., a column-based solution) for the memory. In a column-based solution, the primitives are arranged such that each column includes only one type of primitive. The column-based solution generated in this step uses the minimum number of primitives attainable by a column-based approach. The column-based solution is then modified to reduce multiplexing, e.g., by replacing two primitives that are cascaded in depth with two primitives that are cascaded in width. In some embodiments, the total number of primitives can be reduced by the modification. The resulting physical representation of the memory is then output, and can be utilized, if desired, to create an implementation of the memory targeted to a PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.