Performance variation compensating circuit and method
US7508246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Jan 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.