Self-repairing technique in nano-scale SRAM to reduce parametric failures
US7508697B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2007 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Sep 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process corners, in response to which the SRAM applies adaptive body bias to reduce the number of parametric failures in a die and improve memory yield. Embodiments include circuitry for applying reverse body bias (RBB) to the SRAM array in the presence of a low inter-die Vt process corner, thereby reducing possible read and hold failures, and applying forward body bias (FBB) to the array in the presence of a high inter-die Vt process corner, thereby reducing possible access and write failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.