Buffered memory device
US7508723B2 · kind B2 · utility
8Cited by
19References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2007 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | May 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.