Multi-bit flash memory device including memory cells storing different numbers of bits
US7508732B2 · kind B2 · utility
19Cited by
2References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2007 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Mar 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device comprises an array of memory cells capable of storing different numbers of bits per cell. A page buffer circuit for the flash memory device comprises a plurality of page buffers, each operating during programming, erasing, and reading operations of the memory cells. A control logic unit controls functions of the page buffers in accordance with the number of bits stored in corresponding memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.