System level simulation models for hardware modules
US7509246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Jul 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus automate creation of code for system level simulations from hardware representations, specifically RTL representations. In one approach, individual RTL hardware modules are analyzed to generate code for corresponding system level modules. This is accomplished by taking a mapped netlist for a register transfer level (RTL) representation of the hardware module and converting it to what can be termed a “system level netlist.” This system level netlist contains “system level instances” corresponding to “hardware cells” of the mapped netlist. A mapped netlist includes hardware cells corresponding to programmed hardware units of a target hardware device. The method generates corresponding functional representations (code for system level simulation) from these hardware cells. This functional representation is referred to herein as a system level instance. System level instances are generated for each of the hardware cells in a given hardware module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.