Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
US7509365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | May 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.