Sparse tree adder circuit
US7509368B2 · kind B2 · utility
25Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2005 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | May 15, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.