DRAM remote access cache in local memory in a distributed shared memory system
US7509460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Oct 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.