Advanced processor translation lookaside buffer management in a multithreaded system
US7509476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2007 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the data cache of each of the number of processor cores and configured to pass memory related information among the number of processor cores; a messaging network directly coupled with the instruction cache of each of the number of processor cores and a number of communication ports; and a memory management unit (MMU) coupled with each of the number of processor cores, the MMU having a first translation-lookaside buffer (TLB) portion, a second TLB portion, and a third TLB portion, wherein each TLB portion is operable in several modes, wherein each TLB portion includes a number of entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.