Patent · US Active

Reducing register file leakage current within a processor

US7509511B1 · kind B1 · utility

7Cited by

1References

1Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Harry Barowski · Balingen, DE
Tobias Gemmeke · Santa Clara, US
Jens Leenstra · Nagold, DE
Tim Niggemeier · Laatzen, DE

Key dates

Filing date	May 6, 2008
Grant date	Mar 24, 2009
Priority date	—
Expiry date	May 6, 2028

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for reducing leakage current within a register file of a processor is disclosed. The register file within the processor is partitioned into at least two power domains, and each of the two power domains can be powered independently. At least one of the two power domains includes at least as many physical registers as there are architected registers defined in an instruction set architecture of the processor. In response to an occurrence of an idle condition within the processor, all architected register file entries are consolidated into one of power domains that will not be powered off, and the power domains that does not contain any architected register file entries after consolidating are powered off. Afterwards, in response to a detection of an end of the idle condition, all of the power domains are powered back on.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.