Generating test patterns having enhanced coverage of untargeted defects
US7509600B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Sep 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.