Heuristic clustering of circuit elements in a circuit design
US7509611B2 · kind B2 · utility
3Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | May 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.