Design method and architecture for power gate switch placement and interconnection using tapless libraries
US7509613B2 · kind B2 · utility
22Cited by
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3Claims
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Key dates
| Filing date | Jan 13, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Jan 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these standard cells may be provided by the switch cells or by specialized tap cells. The tapless standard cells may include only a context-sensitive rail, which may be configured to be a virtual ground rail by a power gating connection to a switch cell or by a direct connection to a power supply or ground rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.