Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages
US7509619B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2005 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Aug 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/343
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.