Dummy filling technique for improved planarization of chip surface topography
US7509622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Oct 25, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the “case” of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.