Memory cells in double-gate CMOS technology provided with transistors with two independent gates
US7511989B2 · kind B2 · utility
27Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2007 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Mar 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.