Olivier Thomas
39Patents
8h-index
57Co-inventors
78Inventor score
Filing activity: Jun 19, 1986 → May 31, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8183630B2 | Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT | Electricity | 252 | Active |
| US8013399B2 | SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable | Electricity | 228 | Active |
| US4726701A | Modular shelf assembly | Emerging Cross-Sectional Technologies | 34 | Expired |
| US7511989B2 | Memory cells in double-gate CMOS technology provided with transistors with two independent gates | Physics | 27 | Active |
| US5945162A | Method and device for introducing precursors into chamber for chemical vapor deposition | Chemistry; Metallurgy | 16 | Expired |
| US8502318B2 | SRAM memory cell provided with transistors having a vertical multichannel structure | Electricity | 12 | Active |
| US8116118B2 | Memory cell provided with dual-gate transistors, with independent asymmetric gates | Electricity | 10 | Active |
| US8969967B2 | Self-contained integrated circuit including adjacent cells of different types | Electricity | 9 | Active |
| US5214926A | Device, especially autonomous and portable for extracting heat from a hot source | Mechanical Engineering; Lighting; Heating | 7 | Expired |
| US9093499B2 | Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well | Electricity | 5 | Active |
| US8710671B2 | Multi-level integrated circuit, device and method for modeling multi-level integrated circuits | Electricity | 5 | Active |
| US9542996B2 | Device with SRAM memory cells including means for polarizing wells of memory cell transistors | Electricity | 4 | Active |
| US7787286B2 | SRAM memory with reference bias cell | Physics | 4 | Active |
| US9508434B2 | Programmable-resistance non-volatile memory | Physics | 4 | Active |
| US8399316B2 | Method for making asymmetric double-gate transistors | Electricity | 3 | Active |
| US9190334B2 | SOI integrated circuit comprising adjacent cells of different types | Electricity | 3 | Active |
| US7812410B2 | Suspended-gate MOS transistor with non-volatile operation | Electricity | 3 | Active |
| US7768821B2 | Non-volatile SRAM memory cell equipped with mobile gate transistors and piezoelectric operation | Physics | 3 | Active |
| US7622983B2 | Method and device for adapting the voltage of a MOS transistor bulk | Physics | 3 | Active |
| US10002664B2 | Non-volatile resistive memory cell comprising metal electrodes and a solid electrolyte between the metal electrodes | Physics | 2 | Active |
| US9449688B2 | Device and method for writing data to a resistive memory | Physics | 2 | Active |
| US11110765B2 | Suspension spring saddle | Mechanical Engineering; Lighting; Heating | 2 | Active |
| US8320198B2 | SRAM memory cell with double gate transistors provided means to improve the write margin | Physics | 2 | Active |
| US7928797B2 | Integrated circuit with a power transistor gate bias controlled by the leakage current | Electricity | 2 | Active |
| US10559355B2 | Device and method for writing data to a resistive memory | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.