Die based trimming
US7512507B2 · kind B2 · utility
2Cited by
27References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2006 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Apr 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodiment, the odd and even blocks of each non volatile memory die are erased and then programmed to test the program time. Statistical analysis of the tested program times is performed. Based on this analysis the trim values are determined and programmed into the die. Accordingly, each die on a wafer has its individual trim settings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.