Inter-chip communication system
US7512728B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | May 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The complexity of user designs, the limited capacity of FPGA chips, and the limited number of chip pinouts have resulted in the development of inter-chip communication technology that necessitates the transfer of a large amount of data across a limited number of pins in the shortest amount of time. The inter-chip communication system transfers signals across FPGA chip boundaries only when these signals change values. Thus, no cycles are wasted and every event signal has a fair chance of achieving communication across chip boundaries. The inter-chip communication system includes a series of event detectors that detect changes in signal values and packet schedulers which can then schedule the transfer of these changed signal values to another designated chip. Working with a plurality of signal groups that represents signals at the separated connections, the event detector detects events (or changes in signal values). When an event has been detected, the event detector alerts the packet scheduler. The packet scheduler employs a token ring scheme as follows. When the packet scheduler receives a token and detects an event, the packet scheduler “grabs” the token and schedules the transmi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.