Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
US7512750B2 · kind B2 · utility
12Cited by
17References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Jul 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.