Embedded test circuit for testing integrated circuits at the die level
US7512915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Jun 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.