Method for fabricating shallow trench isolation structures using diblock copolymer patterning
US7514339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2007 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Feb 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3086
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.