Structures and methods to store information representable by a multiple bit binary word in electrically erasable, programmable read-only memories (EEPROM)
US7515465B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2006 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Mar 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply. Using the distinctive threshold voltage associated with the different stored charges, the output voltage from the drain is distinctively recognized and converted back to the original n-bit word. A similar method for a PFET EEP…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.