Memory architecture having local column select lines
US7515501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2007 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | May 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections of memory. Each section of memory having a plurality of memory cells arranged in rows and columns of memory and a plurality of sense amplifiers located in each of the plurality of regions. The sense amplifiers coupled to a respective column of memory. A plurality of column select lines are located in each of the plurality of regions with each column select line coupled to a group of column select switches associated with a section of memory to activate the respective column select switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.