Dynamic input setup/hold time improvement architecture
US7515669B2 · kind B2 · utility
3Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Jun 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system clock. The switching threshold of a second digital buffer is updated. The digital input processed through the second digital buffer is sampled. The sampling is at the falling edge of the system clock. The switching threshold of the first digital buffer is updated. A digital sampling circuit is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.