Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies
US7516306B2 · kind B2 · utility
7Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2004 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Mar 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30098
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.