Processor for computing a packed sum of absolute differences and packed multiply-add
US7516307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2001 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Mar 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed sum of absolute differences (PSAD) instruction having an opcode format to identify a set of packed data operands. The decode unit initiates a sequence of operations on the set of packed data operands in response to decoding the PSAD instruction. An execution unit performs a first operation of the sequence of operations initiated by the decode logic, and a bus provides the execution unit with the set of packed data operands as identified in accordance with the opcode format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.