On-chip data transmission control apparatus and method
US7516382B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2005 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Jul 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4915
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.