Thin semiconductor device package
US7517732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jan 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin semiconductor device package, comprising a thin substrate, at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate, a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.