C4 joint reliability
US7517787B2 · kind B2 · utility
5Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2005 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.