Integrated circuit having pairs of parallel complementary FinFETs

US7517806B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Andres Bryant · South Burlington, US
• William F. Clark, Jr. · South Burlington, US
• David M. Fried · Ithaca, US
• Mark D. Jaffe · Shelburne, US
• Edward J. Nowak · South Burlington, US
• John J. Pekarik · Underhill, US
• Christopher S. Putnam · South Burlington, US

Key dates

• Filing date: Jul 21, 2005
• Grant date: Apr 14, 2009
• Expiry date: May 3, 2026

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/947
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The fi…