Deposition pattern for eliminating backside metal peeling during die separation in semiconductor device fabrication
US7518240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Dec 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer that includes a plurality of groups of active devices or circuits on a first side of the wafer and a patterned electrical contact on the backside of the wafer. Each group consisting of an active device or circuit is intended to be diced into a discrete chip. The backside of the wafer includes a metal layer patterned into discrete spaced-apart deposits that form an electrical contact to the semiconductor and the respective group of active devices. The deposits are not contiguously or laterally connected to each other and function to protect the metal layer from peeling or detaching from the wafer during dicing of the semiconductor wafer into chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.