Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices
US7518425B2 · kind B2 · utility
3Cited by
7References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 5, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.