Multi-level non-volatile memory
US7518912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jul 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.