Pseudorandom noise lock detector
US7519099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/70753
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A device for detecting data synchronization in data communications includes pseudorandom noise (PN) lock circuits (101, 113, 127). The PN lock circuits (101, 113, 127) receive an input data stream (109). Each of the PN lock circuits (101, 113, 127) is time offset with respect to the other PN lock circuits. Each of the PN lock circuits (101, 113, 127) outputs a PN sequence responsive to the input data stream. For each PN lock circuit, there is provided a component (105, 117, 131) for comparing the PN sequence from the respective PN lock circuit to the input data stream, to determine whether the input data stream and the PN sequence are synchronized. An indication (107, 119, 133) that the data is synchronized is provided when the input data stream and the PN sequence are synchronized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.