Patent · US Active

Method and apparatus to test the power-on-reset trip point of an integrated circuit

US7519486B2 · kind B2 · utility

6Cited by

13References

33Claims

0Family size

Assignee

Atmel Corporation · US

Inventors

Philip Ng · Thornhill, CA
Jinshu Son · Saratoga, US
Liqi Wang · Bishop, US
Johnny Chan · Fremont, US

Key dates

Filing date	Mar 31, 2006
Grant date	Apr 14, 2009
Priority date	—
Expiry date	Feb 16, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3004
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.