Input-output device testing
US7519888B2 · kind B2 · utility
6Cited by
59References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Oct 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31715
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Integrated circuit test circuits may include at least an instruction processor and input-output subsystems. Input-output subsystems are segmented together into input-output subsystem segments. Each input-output subsystem includes an analog wrapper circuit (IW-A) operable to connect an input-output port to analog buses and further operable to isolate the input-output port from the buses, an integrated wrapper for delay test circuit (IW-D) operable to control a delay test sequence, and a soft wrapper circuit operable to control the IW-A and the IW-D, the soft wrapper circuit being directed by the instruction processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.