Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry
US7519941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/84
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.