Package having dummy package substrate and method of fabricating the same
US7521289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Jan 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package may include a stack of unit chip packages, and each unit chip package may include a printed circuit board. The printed circuit board may support a semiconductor chip and a connection terminal for connecting to an adjacent unit chip package within the stack. A dummy package substrate may be disposed on the semiconductor chip of the uppermost unit chip package for protecting the semiconductor chip of the uppermost unit chip package. A method of fabricating a package may involve stacking unit chip packages so that the printed circuit board of a lower unit chip package abuts against a solder bump of an upper unit chip package, and stacking a dummy package substrate on the printed circuit board of an uppermost unit chip package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.