Method for fabricating semiconductor device
US7521305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | May 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.