Dual layer stress liner for MOSFETS

US7521308B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Deleep R. Nair · Fishkill, US
• Christopher V. Baiocco · Newburgh, US
• Xiangdong Chen · Irvine, US
• Junjung Kim · Fishkill, US
• Jae-Eun Park · Wappingers Falls, US
• Daewon Yang · Hopewell Junction, US

Key dates

• Filing date: Dec 26, 2006
• Grant date: Apr 21, 2009
• Expiry date: Jun 11, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0223
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.