Method of fabricating semiconductor device having fine contact holes
US7521348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.