Shielding structures for preventing leakages in high voltage MOS devices
US7521741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Nov 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.