DMOS transistor with optimized periphery structure
US7521756B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Jan 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.