Dual stress STI
US7521763B2 · kind B2 · utility
6Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Feb 14, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/908
Abstract
The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.