Chip spanning connection
US7521806B2 · kind B2 · utility
188Cited by
95References
20Claims
0Family size
Inventor
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Jan 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system has a first chip having first semiconductor devices and first electrical connections, a second chip having second semiconductor devices and second electrical connections, and a third chip having third semiconductor devices and third electrical connections, the third chip being stacked on top of and physically spanning at least a portion of each of the first and second chips and being connected to the first and second chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.