Method and system for partially reconfigurable switch
US7521961B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1515
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method of configuring a partially reconfigurable switch includes a pipelined partially reconfigurable switch interconnect may include a desired subset of connections in a switch interconnect, a partial bitstream defined for each of the desired subset of connections stored in a memory such as SRAM serving as a buffer, and a controller for cyclically applying the partial bitstream to the switch interconnect. The controller may determine a connection instance and duration for each client access of the switch interconnect in a synchronous manner. A clear to send (CTS), receive data (RD), destination address, and source address at each client may be sent with each partial bitstream for each desired subset of connections. The partially reconfigurable switch and a plurality of partially reconfigurable slot clients may be formed in a silicon backplane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.